1. Field of the Invention
The present invention relates to three-dimensionally integrated semiconductor devices and, in particular, to semiconductor devices vertically bonded together to form three-dimensional structures.
2. Discussion of the Background
The ability to integrate determines the success of the semiconductor industry. This was first demonstrated with the invention of the integrated circuit (IC). The IC essentially consists of fabrication of electronic components at the surface of the semiconductor wafer followed by interconnection of these components with metalization on top of the components. The dramatic reduction in cost and increase in performance that has resulted from this integration has had a profound economic impact.
Since the invention of the IC, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) achieved. For the most part, this improvement in integration density has come from repeated reduction in minimum feature size which allow more components to be integrated in a given area. Additional improvement has come from increases in wafer size.
These integration improvements are essentially two-dimensional (2-D) in nature, in that the volume occupied by the integrated components is essentially at the surface of semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvement in this 2-D integration, there are physical limits to the density which can be achieved in 2-D. One of these limits is simply the minimum size needed to make these components. Another limit is the significant increase in interconnect requirements between components as the component size is reduced.
Efforts to achieve integration beyond that available with 2-D has been explored and resulted in improvement in chip memory and further semiconductor industry growth. For instance, the trench capacitor uses significant semiconductor volume below the wafer surface and allows more functionality to be achieve in a given chip area. Other efforts, directed at achieving higher levels of integration by increased use of the volume in a given chip area, have recently increased. One approach has been to iterate the integration process by adding semiconductor material on top of the interconnect metalization followed by additional interconnect metalization. Although this potentially results in more components per chip area, it suffers from other problems including significantly increased thermal budgets. In addition, this and other efforts are distinct in that they only use one substrate and then work on one surface of that substrate. Not subjecting the devices to the thermal processes involved in fabricating the interconnect would simplify and enhance the fabrication of the devices.
Another problem results from the lagging of the ability to scale interconnect dimensions compared to scaling device dimensions. Ideally, one wants the critical dimension of a via to be the same as a gate dimension. However, since the scaling of vias lags the scaling of devices, integration density is limited.
Further problems arise when trying to integrate different types of technologies into a single circuit or wafer. BiCMOS is one example. Typically, special processing techniques must be devised to be able to combine the technologies. Processes required for one technology often interfere with processes required for another. As a result, compromises are made. The overall development of the combined technology becomes frozen in time, making flexible integration of the technologies that are being combined very difficult if not impossible. In other words, the most advanced xe2x80x9cbest of breedxe2x80x9d technologies are not combined and evolutions in the technologies cannot be exploited.
Another problem of combining technologies is that customization must occur up front. One must first design the processing to combine the technologies and thus the limitations are built into the device. Again, one cannot easily take advantage of evolutions and improvements in technology since that requires redesigning the processing.
It is an object of the present invention to provide a method and device having high integration density.
It is another object of the invention to provide a method and device where different types of materials may be integrated.
It is a further object of the present invention to provide a method of integrating different types of devices, and a structure comprising the integrated devices.
It is yet another object of the invention to provide a method and device where different types of technologies are integrated.
It is a still further object of the invention to avoid or minimize the thermal budgets in interconnecting devices.
It is yet another object of the invention to allow the integration of the best available technologies without making significant processing compromises.
A still further object is to provide improved interconnection of bonded devices, and between devices and boards, cards and/or substrates.
These and other objects may be obtained by a method of forming an integrated device including the steps of forming a first bonding material on a first semiconductor device having a first substrate, forming a second bonding material on a first element having a second substrate and directly bonding the first and second bonding materials. A portion of the first substrate may be removed to expose a remaining portion of the first semiconductor device, and the integrated device may be mounted in a package.
The first semiconductor device may be connected to the package from an exposed side of the remaining portion of the first semiconductor device. The first semiconductor device may have a substrate with top and bottom sides, with an active area being formed in the top side, and the package may be connected to the first semiconductor device from the bottom side. A second element having a third substrate may be bonded to the remaining portion of the first semiconductor device, the first element may be removed or substantially removed and the semiconductor device may be connected to the package from the top side.
The first semiconductor device may have a plurality of levels of interconnect, and connections may be formed to at least one of the levels of interconnect from an exposed remaining portion side. A plurality of levels of interconnect may also be formed from an exposed remaining portion side. A connection may be made directly to a device element region of the first semiconductor device.
The method according to the invention may also include steps of bonding a first thermal spreading substrate to a first semiconductor device having a device substrate, removing a portion of the device substrate to expose a remaining portion of the first semiconductor device, and bonding a second thermal spreading substrate to the remaining portion of the first semiconductor. A plurality of levels of interconnect may be formed in the first semiconductor device, and connections to at least one of these levels of interconnect may be made using the first or second thermal spreading substrates. The connections to the levels of interconnect may be formed using an areal contacting method and connections may be made directly to device element regions of the semiconductor device.
The method according to the invention may also include steps of directly bonding a first semiconductor device having a first substrate to an element, removing a portion of the first substrate to expose a remaining portion of the first semiconductor device after bonding, wherein the element may comprise one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna and a matching network comprised of passive elements. The remaining portion of the first semiconductor device may be interconnected with the element and a portion of the remaining portion may be removed to expose a portion of the element.
The method according to the invention may also include directly bonding a first component of a system to a second component of the system, and interconnecting the first and second components. The first component may be bonded to a second component having a substrate, at least a portion of the substrate may be removed and the first and second components may be interconnected from the side of the second component from which the portion has been removed. A shielding member, an isolation member or an antenna may be bonded to at least one of the first and second components. The antenna may also be interconnected with at least one of the first and second components. An optical device may be bonded to an electrical device, or a lower-speed higher-density semiconductor device may be bonded to a higher-speed lower-density semiconductor device. The first and second semiconductor devices may be of different technologies. As an example, a microprocessor may be bonded to a high density memory device or, as another example, first and second solar cells may be bonded together.
The method according to the invention may also include attaching a plurality of first elements to a surface of a substrate to form a second element, and directly bonding the second element, from a side to which the first elements are attached, to a third element. The attaching step may comprise directly bonding each of the plurality of first elements to a surface of the substrate. A portion of the second element may be removed after bonding. The first elements may be interconnected with the third element, the first elements may be interconnected using the second element, and the first elements and third element may be interconnecting using at least one of the second and third elements. Recesses may be formed in the second element, and the first elements may be bonded to the second element in the recesses.
As a further embodiment, a method may include steps of forming a first bonding material on a first semiconductor device and forming a second bonding material on a second element. The first and second bonding materials may be directly bonded, and a conductor array may be formed having a plurality of contact structures on an exposed surface of the first semiconductor device. Vias may be formed through the first semiconductor device to the device regions, and interconnections may be formed between the device regions and the contract structures. The conductor array may comprise a pin grid array. The method may further include mating the pin grid array with conductive regions formed on one of a board, card and substrate.
The device according to the invention may include a first device portion comprised of a first device having a first substrate from which the first substrate have been removed, a first bonding material formed on the first device portion, a first element having a second bonding material formed thereon, with the first bonding material directly bonded to the second bonding material. The first device portion may comprise a first solar cell portion and the first element may comprise a second solar cell with a substrate. Interconnections may be formed between the first solar cell portion and the second solar cell from a side of the first solar cell portion from which the first substrate is removed.
The first device portion may comprise a semiconductor device having active elements and the first element may comprise one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. The first device portion may have a first side an opposing second side, an interconnections may be made to the device portion from either the first side or the second side. A shielding member or an isolation member may be directly bonded to one of the first device portion and the first element. An antenna may be directly bonded to one of the first device portion and the first device element and interconnections may be made between the antenna and at least one of the first device portion and the first element.
The first device portion may comprise an optical device and the first element may comprise an electrical device. The first element may also comprise a lower-speed higher-density semiconductor device and the first device portion may comprise a higher-speed lower-density semiconductor device.
The integrated device according to the invention may also include a plurality of first elements each directly bonded to a surface of a substrate, to form a second element, and a third element directly bonded to the second element from a side on which the first elements are bonded to the surface of the substrate. Interconnections may be made between the third element and selected ones of the plurality of first elements, and interconnections may be formed between selected ones of the first elements. The first elements may be disposed in recesses formed in the substrate.
As another embodiment, the device according to the invention may include a device portion containing semiconductor devices having opposing top and bottom sides, a first substrate directly bonded to the top side of the device portion and a second substrate directly bonded to the bottom side of the device portions. Interconnections may be formed to the device portions through either or both of the first and second substrates. Power and ground connections may be formed to the device portions through only one of the first and second device substrates, and signal and clock interconnections may be formed to the device portions through the other of the first and second substrates.
The integrated device according to the invention may also include a plurality of first elements each directly bonded to a surface of a second element. The first elements and the second element may include at least one of semiconductor devices, patterned conductors, antenna elements and impedance matching elements. Vias may be formed in the first elements, and conductive material may be formed in the vias to interconnect the first elements with the second element.
The device according to the invention may also include a first bonding material disposed on a first semiconductor device and a second bonding material disposed on a first element. The first and second bonding materials are directly bonded. A conductive array may be disposed on a exposed surface of the first element having a plurality of conductive regions, and interconnections may be formed between the conductive regions of the array and conductive regions of the semiconductor device. The conductive array may comprise a pin grid array. The second conductive regions may be mated with conductive regions formed on at least one of a board, card and substrate.